1. Field of the Invention
The present invention relates to improvements in packages for integrated power circuits. More particularly, the invention relates to improvements particularly suited for power connects to replace wire bond interconnects in power packaging. In particular, the present invention relates specifically to self-healing phase changing power connections for high temperature operating environments.
2. Description of the Known Art
As will be appreciated by those skilled in the art, integrated circuits and power circuit packages are known in various forms. These include: U.S. Pat. No. 7,232,710, issued to Hsu, et al. on Jun. 19, 2007 entitled Method of making cascaded die mountings with springs-loaded contact-bond options; U.S. Pat. No. 6,793,502, issued to Parkhill, et al. on Sep. 21, 2004 entitled Press (non-soldered) contacts for high current electrical connections in power modules; U.S. Pat. No. 6,930,385, issued to Hsu, et al. on Aug. 16, 2005 entitled Cascaded die mountings with spring-loaded contact-bond options; U.S. Pat. No. 5,604,377, issued to Palagonia on Feb. 18, 1997 entitled Semiconductor chip high density packaging; U.S. Pat. No. 4,891,686, issued to Krausse, III on Jan. 2, 1990 entitled Semiconductor packaging with ground plane conductor arrangement; U.S. Pat. No. 5,514,604, issued to Brown on May 7, 1996 entitled Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making; U.S. Pat. No. 5,665,996, issued to Williams, et al. on Sep. 9, 1997 entitled Vertical power mosfet having thick metal layer to reduce distributed resistance; U.S. Pat. No. 5,767,567, issued to Hu, et al. on Jun. 16, 1998 entitled Design of device layout for integration with power mosfet packaging to achieve better lead wire connections and lower on resistance; U.S. Pat. No. 6,249,041, issued to Kasem, et al. on Jun. 19, 2001 entitled IC chip package with directly connected leads; U.S. Pat. No. 7,057,273, issued to Harnden, et al. on Jun. 6, 2006 entitled Surface mount package; U.S. Pat. No. 7,215,012, issued to Harnden, et al. on May 8, 2007 entitled Space-efficient package for laterally conducting device; U.S. Pat. No. 7,332,757, issued to Kajiwara, et al. on Feb. 19, 2008 entitled MOSFET package; U.S. Pat. No. 7,394,150, issued to Kasem, et al. on Jul. 1, 2008 entitled Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys; U.S. Pat. No. 7,449,370, issued to Tanaka on Nov. 11, 2008, entitled Production process for manufacturing such semiconductor package; and U.S. Pat. No. 7,485,954, entitled Havanur on Feb. 3, 2009 entitled Stacked dual MOSFET package. Each of these patents is incorporated by reference in their entirety.
Typical circuit or chip packages use wire bond interconnects which is one of the main limitations of today's state-of-the-art power interconnects. Wire bond interconnects introduce major inductance parasitics into the power flow; severely limiting switching frequencies, causing di/dt and dv/dt overcurrent and overvoltage waveforms within the power modules, and causing substantial bus ringing that must be minimized via bulky DC-link capacitors. Such electrical issues at the switch and module level magnify stresses across the power transistor, negatively impacting long term reliability of the semiconductor. Furthermore, one of the primary failure mechanisms of power modules can be traced back to environmental effect such as physical and thermal-stress of the wire bond interconnects. These wire bonds are highly susceptible to mechanical fatigue failure as the packaging undergoes thermal and power cycling because the wires become stressed at the substrate interface, die interface, bond heel, and bond knee, all of which become potential points for fracture and failure. Power transistor wire bonds must typically carry electrical current in the range of 10 s of amps or more. This often results in substantial current crowding at the knee or heel of the bond, and at the die-pad interface which again, results in potential points of failure due to localized hot spots and stresses. All of these issues become further exacerbated with the transition to wide bandgap power devices, which are capable of high temperature operations well in excess of 250° C. and these limitations severely limit the 600+° C. that is theoretically achievable. The mechanical fatigue from thermal cycling becomes multiplied by orders of magnitude at these temperatures, and the life-time reliability (i.e. the theory behind accelerated life testing for standard electronics packaging) of a wire bond interconnect begins to drop exponentially. Such wire bond interconnects will clearly have difficulty achieving long term confidence and reliability in wide bandgap power systems, and even in today's low temperature silicon based systems they cannot achieve the 10+ year reliability targets set out by the department of energy for many industry platforms (automotive, solid-state smart grid, etc.).
In high frequency IC applications, wire bonds were eliminated years ago and replaced with new advanced technologies such as flip-chip and ball grid arrays. These processing techniques have barely penetrated into the power switch market, primarily due to the fact that power devices (unlike high frequency ICs) are vertical devices requiring both top-side and backside electrical connections. Flipping the device still leaves the power transistor backside exposed and requiring an electrical connection. Developers have shown metal tabs, straps, and solder contacts all to be feasible for this top-side contact, but they suffer from reliability problems on par with or worse than wire bonding. The most successful wire bondless power package today is the “press pack” or puck, which implements a high pressure contact. This puck is utilized almost exclusively in the high voltage solid-state switching arena where double-sided cooling is an essential requirement. See U.S. Pat. No. 5,346,859, issued to Niwayama on Sep. 13, 1994 entitled Method for fabricating a full press-pack type semiconductor which is hereby incorporated by reference in its entirety.
As semiconductor power switch capabilities continue to improve significantly in current density, switching speeds, temperature of operation, voltage blocking, and integration; the power electronic system level performance “choke-point” is increasingly traced back to the packaging of the power switch or module. It simply is not achievable for today's commercial high voltage power modules to operate at significantly high switching speeds or frequencies. The energy losses in the power module parasitics are too high, and this in turn limits the capability of the entire power electronic converter system. Module power densities have reached their limits with today's thermal management strategies, which again, are heavily dependent upon the module packaging technology. With the introduction of advanced wide bandgap materials, today's power modules cannot achieve the junction temperatures conducive to taking full advantage of the thermal performance of these new devices. Finally, present power packaging technologies will not survive the new long term reliability requirements demanded by newer fields like automotive and smart grid, which absolutely must deliver reliable service to their customers at all times. It is critical that new investments be made, now, into revolutionary power packaging ideas that can overcome many of these debilitating weaknesses, or smart power electronics will remain elusive.
From these prior references it may be seen that the prior art is very limited in its teaching and utilization, and an improved connection is needed to overcome these limitations.